// module led_ctrl(
//     input   wire        sys_clk     ,
//     input   wire        sys_rst_n   ,

//     output  reg  [3: 0] led
// );
    


//     parameter TIME_500ms = 25_000_000;
//     reg     [24:0]      cnt_500ms       ;//计数500ms 刷新时间
//     wire                add_cnt_500ms   ;
//     wire                end_cnt_500ms   ;

//     //500ms计数
//     always @(posedge sys_clk or negedge sys_rst_n)begin
//         if (!sys_rst_n) begin
//             cnt_500ms <= 25'b0;
//         end
//         else if(add_cnt_500ms)begin
//             if(end_cnt_500ms)begin
//                 cnt_500ms <= 25'b0;
//             end
//             else begin
//                 cnt_500ms <= cnt_500ms + 1'b1;
//             end
//         end
//         else begin
//             cnt_500ms <= cnt_500ms;
//         end
//     end
//     assign add_cnt_500ms = 1'b1;
//     assign end_cnt_500ms = add_cnt_500ms && cnt_500ms == TIME_500ms-1 ;

//     always @(posedge sys_clk or negedge sys_rst_n) begin
//         if (!sys_rst_n) begin
//             led <= 4'b0000;
//         end
//         else if(end_cnt_500ms)begin
//             led <= ~led;
//         end
//         else begin
//             led <= led;
//         end
//   end


// endmodule


module led_ctrl #(parameter TIME_0_5S = 25_000_000)(
    input               sys_clk     ,
    input               sys_rst_n   ,
    output  reg [3:0]   led     
);
    reg     [24:0]      cnt     ;
    wire                add_cnt ;
    wire                end_cnt ;
    reg     [2:0]       cnt1;
    wire                add_cnt1;
    wire                end_cnt1;

    always @(posedge sys_clk or negedge sys_rst_n)begin
        if(!sys_rst_n) begin
            cnt <= 25'b0;
        end
        else if(add_cnt) begin
            if(end_cnt) begin
                cnt <= 25'b0;
            end
            else begin
                cnt <= cnt+1'b1;
            end
        end
        else begin
            cnt <= cnt;
        end
    end

    // 异步复位
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(!sys_rst_n)begin
            cnt1 <= 3'b0;
        end
        else if(add_cnt1) begin
            if(end_cnt1)begin
                cnt1 <= 3'b0;
            end
            else begin
                cnt1 <= cnt1 + 1'b1;
            end
        end
    end

    always @(posedge sys_clk or negedge sys_rst_n)begin
        if(!sys_rst_n)begin
            led <= 4'b0;
        end
        else begin
            case (cnt1)
                3'b000 : led <= 4'b0001;
                3'b001 : led <= 4'b0010;
                3'b010 : led <= 4'b0100;
                3'b011 : led <= 4'b1000;
                default: led <= led;
            endcase
        end
    end


    assign add_cnt = 1'b1;
    assign end_cnt = add_cnt && cnt == TIME_0_5S - 1;
    assign add_cnt1 = (cnt == TIME_0_5S-1);
    assign end_cnt1 = add_cnt1 && cnt1 == 3'b111;

endmodule